Intel details U.S. advanced packaging push for larger AI chiplet systems

Intel used a July 29 newsroom post to highlight how its U.S. advanced packaging work is being positioned for the next phase of AI semiconductor design. The company says the industry is moving beyond single, monolithic chips toward multi-chip packages that connect specialized chiplets so they can behave like one high-performance system.

The focus is Intel Foundry's operations in Rio Rancho, New Mexico, where Intel says its advanced packaging technologies are expanding the practical package size available to chip designers. According to Intel, the site is scaling packages to eight times the industry standard today, with a roadmap to more than 12 times by 2028. The company frames that extra package area as important for AI accelerators, where designers need to place compute tiles, memory interfaces and other functions close together without being constrained by a single reticle-sized die.

Why packaging matters for AI hardware

Advanced packaging is increasingly a competitive battleground because AI systems depend on moving data efficiently between processors and high-bandwidth memory. Intel's post describes two core approaches: Foveros, which stacks and connects chiplets through a silicon interposer, and EMIB, which uses small embedded silicon bridges where high-speed links are needed. The company says EMIB can reduce the need for larger and more expensive interposer layers while still letting neighboring dies communicate at high speed.

Intel also described EMIB-T as a 2026 development that adds channels through the bridge to deliver power more directly to chips. In Intel's telling, that can improve power efficiency and signal routing for packages that use the latest high-bandwidth memory technologies. Those claims matter because power delivery, thermals and data movement are now as central to AI accelerator performance as the raw transistor density of the compute silicon itself.

The announcement is also a foundry positioning message. Intel says the New Mexico operation has grown from 25 employees in 1980 to 2,700 employees and 500 suppliers, and it argues that U.S.-based packaging capacity can help customers assemble large AI engines from chiplets built on different designs or process nodes. That flexibility is the strategic point: if more AI hardware is built as a system of tiles, packaging becomes a central part of the product rather than a back-end manufacturing detail.

Sources

• newsroom.intel.com

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